MEEP (MareNostrum Experimental Exascale Platform) is a flexible FPGA-based emulation platform that will explore hardware/software co-designs for Exascale Supercomputers and other hardware targets, based on European-developed IPs. Particularly, MEEP’s ambition is to play two important roles within the Exascale computation paradigm:
1) Become an evaluation platform of pre-silicon IP and ideas, capable of balancing speed and scalability.
2) Become a software development and experimentation platform to enable software readiness for new hardware designs. MEEP will accelerate software maturity, compared to the limitations of software simulation approaches, since IPs will be tested and validated before moving to silicon, considering a realistic componentization characterization and running them under their targeted execution contexts; which means saving time and money.
Along its lifetime, MEEP will deliver a series of Open-Source IPs, when possible. They will be able to be used for academic purposes, and/or be integrated into a functional accelerator or cores for traditional and emerging HPC applications.
The MEEP project’s first target accelerator is a design that could be available in 5 years and would be realized as a collection of chiplets with High Bandwidth Memory. The goal is to map as much of a single accelerator to a single FPGA and compose a system of multiple FPGAs or emulated accelerators. Based on this approach, it is possible to focus on emulation speed vs overall emulated accelerator performance. As a Proof of Concept (PoC), the first step is mapping a scaled-down functional and operative approximation of the emulated accelerator that will fit in the FPGA, which contains the main accelerator components. In addition, the MEEP project provides a set of software tools that translate the diverse nature of HPC applications into executables that run on top of the emulated hardware accelerator.