MEEP will provide a foundation for building European-based chips and infrastructure to enable rapid prototyping using a library of IPs and a standard set of interfaces to the Host CPU and other FPGAs in the system using the FPGA shell. In addition to RISC-V architecture and hardware ecosystem improvements, MEEP will also improve the RISC-V software ecosystem with an improved and extended software tool chain and software stack, including a suite of HPC and HPDA (High Performance Data Analytics) applications.
From a high-level perspective, MEEP is defined as a layered structure, such as it is depicted below. There exist direct dependencies among consecutive vertical layers; whereas the vertical layer is transversal to all the rest.
The above structure contextualizes the scope of each layer and the close relationship among contiguous layers, at the same time. HPC applications (first layer on top) need software tools (second layer) to transform programs into something readable and executable on the emulation platform (third layer), according to the characterization of the accelerator architecture (fourth layer).
Each layer has its own responsibility, and all of them might be analyzed using profiling and performance monitoring tools. In particular:
- HPC Applications layer studies and analyzes different kinds of applications, considering their workloads, data distribution and dependencies, level of parallelism, programming languages, etc.
- The Software toolchain layer provides the required software ecosystem to exploit hardware capabilities. It includes the software stack, from the operating system (at the bottom) to several HPC runtimes (at the top).
- The Emulation Platform layer enables the possibility of executing HPC applications on top of the Accelerator Architecture, using the information received from the Software toolchain layer.
- The Accelerator Architecture layer defines the accelerator components, their connectivity and functionality.
- The Profiling and performance monitoring layer gives some feedback in terms of applications memory access pattern.
Read more details on the MEEP platform layers here.
MEEP development phases
In order to deal with MEEP complexity and dimension, its development will be afforded in two main phases:
Phase 1: It will work with a portion of the architecture to a single FPGA, a single instance of the emulation platform. The development of this phase will use the Xilinx Alveo U280 data center accelerator cards. The idea behind this experimental work is being able to demonstrate the viability of MEEP as an FPGA-emulation platform.
Phase 2: A bigger and more complex system will be developed in which 4 cards will be connected to facilitate early FPGA-to-FPGA communication development as well. The idea is to scale the system beyond what can be done with these cards in a denser form factor. Therefore, the OAM platform will be used to place up to 8 OAM FPGA devices in a Universal Base Board UBB chassis.