After MEEP, the project successfully identified and uploaded 16 Key Exploitable Results (KER, defined at the bottom of the page) to the Horizon Results Platform.
| Design&Verification (DV) CORE | UVM environment based on Lagarto Ka core developed in BSC |
| MEEP Accelerator Integration Tool (AIT) | It is a tool to automatize generating bitstreams of customized designs based on several predefined design templates using the Xilinx toolchain. It is based on the OmpSs@FPGA programming model. |
| Aurora DMA design | New design of Aurora IP from Xilinx for Alveo cards that communicates two boards, adding an AXI DMA and external DDR4 memory |
| DVINO (scalar core +VPU) | MEEP Dvino is divided into two parts: Dvino (Drac Vector IN-Order integrating a Lagarto scalar core with a Hydra Vector Processing Unit (VPU).) FPGA Shell, where it encapsulates all the Xilinx IPs and related logic for the hardware platform. The other part, the Dvino ASIC top, contains the RTL of Lagarto, VPU, caches and peripherals. |
| MEEP FPGA Shell | The shell is meant to be a static perimeter architecture, which guarantees that the inside accelerator package can be interchangeable with any other package when meeting a defined I/O interface between the shell and the accelerator package. |
| ProNoC | It is an open-source RTL implementation of state-of-the-art NoC that provides many features configurable using Verilog parameters. This emerging interconnect infrastructure addresses the scalability limitation of a conventional shared bus architecture for many-core system-on-chip, especially suited for FPGA. |
| MEEP Vector Processing Unit (MEEP VPU) | Vector processor Units (VPUs) are well-known accelerators because they can exploit data-level parallelism with single-instruction multiple-data. VPUs have applicability in various application domains such as machine learning, scientific simulations, etc. The gains in performance from a VPU are realized majorly through a deeply pipelined data path, predicated execution, multiple lanes of execution and features such as chaining. The capabilities and applicability of a VPU are greatly extended in the MEEP project with a suitable memory path and a data path to support vector operations with sparse and very long vector operands, considering the requirements of various practical vector operations. |
| Systolic Array (SA) Shell | The SA Shell is a stand-alone module that enables easier integration of specific systolic array accelerators into the top-level system. In MEEP's architecture, the SA Shell is integrated into the VAS tile. |
| Systolic Array for image and video processing (SA-HEVC) accelerator | SA-HEVC is a systolic array accelerator specialized for image and video processing based on the HEVC/H.265 video coding standard. |
| Systolic Array Neural Network (SA-NN) accelerator | Systolic Arrays (SA) provide efficient mechanisms for processing various data, from image and video processing to neural networks. Like the VPU, the SAs require some management and memory access provided through the same interfaces as the VPU. |
| Accelerated Computing and Memory Engine (ACME) Emulated Accelerator | ACME_EA (Accelerated Compute and Memory Engine Emulated Accelerator)+ is the self-hosted accelerator conceived in MEEP and is envisioned as a collection of chiplets composed together in a module. MEEP aims to capture the essential components of one of the chiplets in the FPGA and replicate that instance multiple times. |
| COYOTE | offers the speed and flexibility to compare configurations within feasible simulation times and implementation efforts before committing to FPGA emulation. |
| MEEP compilers toolchain | The compiler infrastructure used in the MEEP project is built on top of the LLVM-based compiler. |
| MEEP Software stack base release | This software suite contains the operating systems (OS) layer section based on Fedora Linux and additional recipes to install/update supporting OS packages and use the available container images. |
| MEEP platform infrastructure – Full cluster, including the full stack | The emulation FPGA cluster platform is installed with an "easy-to-use" SW Stack (Fedora OS, LLVM compilers..) to test, configure, and run HPC apps easily. |
| Design and Verification (DV) ACME_VPU | Testbench was used to verify the RTL design extension over the EPI VPU within the MEEP ACME_VPU using UVM and functional coverage methodology. |
Definitions:
- Result: Refers to any concrete or abstract outcome of the action, encompassing data, knowledge, and information in any form or nature, regardless of their protectability. This includes any associated rights, including intellectual property rights, generated within the action.
- KER: Denotes the primary and noteworthy result that has been chosen and given priority due to its substantial potential for "exploitation," which entails utilizing and deriving benefits downstream in the value chain of a product, process, or solution. Alternatively, it can serve as a significant input for policy-making, further research, or educational purposes.