3rd Workshop on RISC-V and OpenPOWER in HPC

RISC-V and OpenPOWER architectures, together with the introduction of new ISA extensions, have gained traction in the domain of High-Performance Computing (HPC). In addition, environmental awareness and the increasing demand for computational and storage capabilities put a spotlight on the power consumption of large-scale supercomputing centres.

One of the main goals of the workshop is to create awareness and engagement around the open-source initiatives (including the target Open Architectures aforementioned). That will allow collaborative activities between academia and the industry and create placeholders for ongoing international research projects and follow-up their evolution along the time.

The workshop will include technical presentations that contribute to developing a fully open-source ecosystem, from software to hardware and build the next generation of HPC systems on top of it.

Since this year would be the third year that this workshop is being held, it is an attempt to establish an event-to-be concerning open architectures and HPC. Last year we had a long list of distinguished speakers, and we are hoping to invite a healthy mix to maximize the impact of the exchange of advice, opinions and contacts.

Register for attendance (closed)

Registering for attendance will require to fill the registration form. The register is free and will provide access to the full program. Connection details will be provided before the workshop kick-off on Monday, June 27th.

Call for Participation (closed)

Participating in this workshop will require you to submit a brief description of your talk.

Important dates:

• Submission deadline: May 15th, 2022
• Submission deadline (extended): May 25th, 2022.
• Notification of acceptance:  June 1st, 2022
• Notification of acceptance: June 13th, 2022
• Workshop event: June 27th, 2022 (online event)

Program

08:30 - 08:35 EST / 14:30 - 14:35 CEST Workshop Message
Host: Teresa Cervero

• Organizers' Welcome

Invited talks

08:35 - 09:05 EST / 14:35 - 15:05 CEST

• Calista Redmond (RISC-V International)
• James Kulina (OpenPOWER foundation)

Session 1

09:05 - 10:35 EST / 15:05 - 16:35 CEST
Technical talks  (RISC-V & OpenPower topics)
Chair: Alexander Fell

• Coherent Distributed Computing: ZOLC, SVP64, OpenCAPI  (Luke Leighton - Libre-SOC)

• Custom Chip Design: Open Source Chip Development Using OpenPOWER Microwatt  (Satyadhyan Chickerur - KLE Technological University)

• OpenMP and RISC-V for Green SuperComputers (Bernard Goossens - Université de Perpignan, France)

• Towards the Development of Custom RISC-V Accelerators for HPC and Scientific Instruments  (Kazutomo Yoshii - Argonne National Laboratory)

• Q&As

10:35 - 10:45 EST / 16:35 - 16:45 CEST Coffee break (10')

Session 2

10:45 - 11:55 EST / 16:45 - 17:55 CEST
Technical talks (RISC-V & OpenPower topics)
Chair: Xavier Teruel

• RISC-V in HPC EU Projects (John D. Davis - Barcelona Supercomputing Center)
• Is RISC Risk-Free? - An insight on RISC-V & OpenPOWER Cores (Manikandan Nagarajan - SASTRA University)
• Deep Learning Inference: Manual or Automatic Generation of Optimized Kernels for RISC-V (Enrique S. Quintana-Orti - Universitat Politecnica de Valencia)
• Q&As

Session 3

11:55 - 12:55 EST / 17:55 - 18:55 CEST
Panel discussion (45')
Chair: Osman Unsal (BSC)

Panellists:

John Davis (RISC-V SIG-HPC Chair),

Bernard Goossens (Université de Perpignan),

Abhinandan S.P. (National Institute of Engineering)

Alex Bradbury (Igalia)

• Block 1: The Open ISAs Roadmap: Past, Present and Future (25')
• Block 2: Open ISAs interactions with stakeholders: Academia, Industry and HPC community (25')
• Wrap-up / Questions (10’)

12:55 - 13:00 EST / 18:55 - 19:00 Workshop farewell (5')

All presentations are available in the links above (titles).

For further details or requiring clarifications, you can contact rvop-chairs@bsc.es