As part of MEEP's activities during the first project period, the design team of the University of Zagreb Faculty of Electrical Engineering and Computing is responsible for designing and implementing the major building framework for the experimental accelerator platform: Systolic Array Shell (SA Shell).

The SA Shell is a stand-alone module that enables easier integration of specific systolic array accelerators into the top-level system. In MEEP's architecture, the SA Shell is integrated into the VAS tile.


Figure 1. Draft SA Shell architecture
Figure 1. Draft SA Shell architecture



As shown in figure 1 (above), the SA Shell consists of several components:

  • Systolic Array Accelerator (SAA): The processing element of the SA Shell. It provides specific functionality to the SA Shell.
  • Control/Status Register(s) (CSR): Store(s) additional information and configuration of the Systolic Array Accelerator. The number of CSR is specific to the accelerator implemented in the SA Shell.
  • MicroEngine(s): The shell is positioned between ACME Scalar Core and local scratchpad memory. Hence, MicroEngines are one-way DMA-like devices that load and store data from and to the Scratchpad. The number of MicroEngines is defined by a specific Systolic Array Accelerator that is implemented in SA Shell and should coincide with the number of input operands and results.
  • OVI interface: The OVI interface decoder is used for decoding SA instructions that are issued through the OVI interface. 

The above activities are aligned with activities carried out by BSC and Tübitak teams to develop an integrated MEEP processing architecture.

As a follow-up design task, UNIZG-FER will design special systolic accelerators for AI and video processing that will use the SA Shell and demonstrate the performance of the solution in various target technologies.