MEEP was featured in a RISC-V press release titled "RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption, and More" on 8 December 2020.
The project is part of a list that features notable examples of RISC-V adoption in 2020. More specifically, MEEP has developed Coyote, a performance modeling tool to provide an execution-driven simulation environment for multicore RISC-V systems with multi-level memory hierarchies.
Moreover, MEEP is a RISC-V member and John Davis, MEEP's coordinator, is Chair of the RISC-V Special Interest Group: High-Performance Computing (HPC). As such, he also participates in the RISC-V Technical Steering Committee (TSC): Strategy, escalations, group and chair, preliminary charter approvals, ratification, etc.
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.