2nd workshop on RISC-V and OpenPOWER in HPC at the ICS International Conference on Supercomputing 2021
Abstract
With the introduction of vector extensions to open instruction set architectures (ISA), the already high interest in those architectures, both academically and industrial, gained traction also in the domain of High-Performance Computing (HPC). In addition, environmental awareness and the increasing demand for computational and storage capabilities put a spotlight on the power consumption of large-scale supercomputing centers. Multiple groups published processors targeting various scenarios such as optimizations for the underlying hardware, but are also addressing specific applications and toolchains. The purpose of this workshop is to provide an overview of the advancements and challenges in open ISAs such as RISC-V and how relevant those discoveries are in the HPC domain. In addition, apart from the actual architecture, also the surrounding environment needs to be taken into consideration. Hence, the workshop will also cover topics including toolchains, applications, and simulations.
As a new and unique field, that receives more attention are topics covering security, data integrity, fault-tolerance, and reliability. Side-channel attacks on RISC-V architectures in the context of HPC seem to be an interesting addition.
Since this year would be the second year that this workshop is being held, it is an attempt to establish an event-to-be with respect to open architectures and HPC. Last year we had a long list of distinguished speakers and we are hoping to invite a healthy mix to maximize the impact of the exchange of advice, opinions, and contacts.
Program
8:30-8:55 EDT/14:30-14:55 CEST Welcome and MEEP (John Davis)
Session 1 (Simulators/Emulators)
9:00-10:30 EDT/15:00-16:30 CEST
- 'Cavatools: Parallel Architecture Simulator for RISC-V.' Speaker: Peter Hsu (BSC).
- 'RISC-V in Sail: A formal and executable specification of RISC-V.' Speaker: Alasdair Armstrong (University of Cambridge).
- 'Comprehensive life cycle of mixed testing, from HDL to gates.' Speaker: Luke Leighton (LibreSOC).
Coffee break
Session 2 (Toolchain)
10:45-12:15 EDT/16:45-18:15 CEST
- 'HDL layout (ASIC) Layout with Coriolis2.' Speaker: Jean-Paul Chaput (Sorbonne University).
- 'SPEC CPU 2017 on RISC-V: war stories of a compiler and performance engineer.' Speaker: Philipp Tomsich.
- 'OpenRAM.' Speaker: Dr. Matthew Guthaus (University of California, Santa Cruz).
Lunch break
Session 3 (HW for HPC)
13:00-15:00 EDT/19:00-21:00 CEST
- 'Boost your high bandwidth data acquisition by adding OpenCAPI and memory coherency to FPGA.' Speaker: Mr. Bruno Mesnet (IBM Power System).
- 'Contributing to the open RISC-V ISA through novel eProcessor hardware.' Speaker: Nehir Sonmez (BSC).
- 'OpenHW CORE-V Cores Roadmap.' Speaker: Davide Schiavone.
- 'Designing and implementing SVP64, adding Cray-style Vectors to OpenPOWER.' Speaker: Luke Leighton (LibreSOC)
- 'Decoupling Compute from Memory, Storage & IO with OMI, the Open Memory Interface.' Speaker: Allan Cantle (Nallasway).
Coffee break
Session 4 (Security/Reliability)
15:15-16:45/21:15-22:45 CEST
- 'Security Vulnerabilities in Modern Power Management for High-Performance Computing Systems.' Speaker: Dr. Jawad Haj-Yahya (ETH Zurich).
- 'Ownership of Neural Networks through Watermarking: Vulnerabilities and Robustness' (video). Speaker: Nandish Chattopadhyay (Nanyang Technological University).
- 'Opentitan, the Technology and the Community.' Speaker: Dr. Dominic Rizzo (Google).
Wrap up
An overview of the state of OpenPOWER and RISC-V in the HPC domain and a vision of the future
17:00-17:30 EDT/23:00-23:30 (CEST)
17:00-17:15 EDT
- 'OpenPOWER.' Speaker: James Kulina (OpenPOWER).
17:15-17:30 EDT
All presentations are available in the links above (titles).