Toulouse ,France
Final Date

Event webpage:

Place: Toulouse (France)
Date: January 16th, 2023 (Cassiopeé room)
Format: Full-day workshop at HiPEAC 2023 conference (January, Monday 16th)

  • Invited talks, gathering experts from academia and industry to foster discussions
  • Panel sessions to discuss the present and future of RISC-V in Europe mainly focused on the HPC domain.



Europe has a renewed focus on digital autonomy, especially for High-Performance Computing (HPC). As part of this effort to achieve technology sovereignty and independence, there has been a clear commitment to promoting and adopting the open-source RISC-V ISA for developing new architectures. However, the current state of the ecosystem does not support this goal. Sometimes this is because of the immaturity of the SW/HW toolchain or the rapid demand for solving more and more complex challenges associated with traditional and new domains, but also environmental awareness and the increasing demand for computational and storage capabilities put a spotlight on the power consumption of large-scale supercomputing centres.

One of the main goals of the workshop is to create awareness and engagement around the European RISC-V initiatives in HPC, bridge the gap between research and industry, and leverage the current resources to create together a path for defining, developing, and building European hardware and software services, tools, and components. There is a special interest in understanding the role that the HW/SW open-source ecosystem and its community play here.

The workshop will include technical talks that contribute to defining state of the art in HPC, defining the future European HPC roadmap, developing a fully open-source ecosystem from software to hardware, and building the next generation of HPC systems. 


Scope and objectives

The purpose of this workshop is to provide an overview of the current advancements and challenges in the RISC-V ISA, how relevant those discoveries impact the HPC domain and discuss the perspective of the European RISC-V HPC landscape.

The workshop will cover all the different levels: from the general RISC-V landscape to the specific impact of each of the individual components. Hence, the event will include topics like software toolchains, applications, simulations, and architectural features.

To be more specific, this workshop has the following goals:

  • Make the audience know the players (research and industry) of those initiatives
  • Create awareness and engagement on current projects/activities in HPC
  • Create a clear picture of the current state-of-the-art on RISC-V HPC
  • Perspective of RISC-V in HPC (including the whole ecosystem)
  • Strengths and weaknesses of the SW/HW ecosystem
  • Highlight the role of the open-source ecosystem

Topics of Interest

  • Processors and accelerator architecture extensions.
  • Memory hierarchy.
  • NoC communication.
  • CAD/EDA Tools.
  • Quality assurance: verification and testing.
  • Simulators and emulators.
  • Operating System (e.g., hypervisor), compilers and runtimes.
  • Containerization and virtualization support.
  • Optimized libraries (linear algebra, data analytics, etc.).
  • Performance Analysis tools and methodologies.
  • Scientific domain applications.
  • Data analytics workloads (AI, ML, DL).
  • HPC Application workflows.

... or any topic related to Open Architecture and HPC!


Registration for attendance:

Registering for attendance will be open on November 1st through the HiPEAC webpage:

Target audience

Anyone interested in the current efforts carried out worldwide on the Open hardware ecosystem based on RISC-V in the context of High-Performance Computing.





10:00 - 10:15

Workshop welcome & Intro to the EU projects (John SIG-HPC)

10:15 – 11:00

Research/Academia Panel: “European RISC-V landscape. A research view (EU Projects)”

Chair: Stephano Cetola (RISC-V Int.)


Panelist 1: Filippo Mantovani (BSC) - EPI 

Panelist 2: John Davis (BSC) - MEEP & eProcessor

Panelist 3: Carlos Puchol (BSC) - EUPilot

Panelist 4: Massimo Celino (ENEA) - TEXTAROSSA

Panelist 5:Carles Hernández (UPV) -  SELENE 

11:00 – 11:30 

Coffee break (30’)

11:30 - 13:00

Tech session 1: SW Stack

Chair: Vicenç Beltrán (BSC)


Stefan Wallentowitz (UM)

Konrad Schwarz (Siemens) 

Nick Kosidifidis (Forth) (FORTH)

Roger Ferrer (BSC)

Wrap-up (10’)

13:00 – 14:00


14:00 - 15:30

Tech session 2: HW Stack  

Chair: Teresa Cervero (BSC)


Davide Schiavone (OpenHW Group)

Miquel Moretó (BSC)

Jon Taylor (Imperas)

Elias Perdomo (BSC)

Wrap-up (10’) 

15:30 - 16:00

Coffee break (30’)

16:00 - 16:45

Tech. Session 3: RISC- V lab and SDV

Chair: (TBC)


Filippo Mantovani (BSC)

Stephano Cetola (RISC-V- RISC-V Lab Training (20’)

Wrap-up (5’)

16:45 – 17:30

Industrial Panel: “European RISC-V in HPC prospective” 


Chair: Miquel Moretó (BSC)


Panelist 1. Jon Taylor (Imperas)

Panelist 2. Michael Chapman (Cortus)

Panelist 3. Roger Espasa (SMD)

Panelist 4. Zdenek Prikryl (Codasip)


For further details or require clarification, you can contact