Challenges and Opportunitiesfor RISC-V Architectures towards Genomics Workloads. Gonzalo Gómez, Aaron Call, Xavier Teruel, Lorena Alonso, Ignasi Moran, Miguel Ángel Pérez, David Torrents, Josep Ll. Berral. Universitat Politècnica de Catalunya. Barcelona Supercomputing Center. Institut Català de Recerca i Estudis Avançats
PublicationJohn D. Davis. European HPC RISC-V Roadmap Workshop HiPEAC 2023
Event reference: https://meep-project.eu/events/hipeac-workshop-european-risc-v-hpc-roadmap
Elias Perdonomo. Flexible and powerful FPGA-based emulation platform. MEEP FPGA-Shell.
Event reference: https://meep-project.eu/events/hipeac-workshop-european-risc-v-hpc-roadmap
Roger Ferrer Ibáñez. LLVM, the RISC-V Vector Extension and its vector length.
Event reference: https://meep-project.eu/events/hipeac-workshop-european-risc-v-hpc-roadmap
MareNostrum Experimental Exascale Platform. EuroHPC Summit 2023. Francelly K. Cano Ladino (BSC-CNS)
RepositoryOptimizations for very long and sparse vector operations on a RISC V VPU: a work in progress
Gopinath Mahale, Tejas Limbasiya, Muhammad Asad Aleem, Luis Plana, Aleksandar Duricic, Alireza Monemi , Xabier Abancens Calvo, Teresa Cervero and John D. Davis
John D.Davis. F4HD: The Future of FPGAs in HPC and Datacenters. Seeing the Future with FPGAs.
Event reference: https://meep-project.eu/events/hipeac-workshop-european-risc-v-hpc-roadmap
What is MEEP? HiPEAC en Toulousse. Elias Perdomo (BSC-CNS).
MEEP poster. A RISC V VPU for Very Long and Spa.rse Vectors
MEEP Poster